Semiconductor structure

ABSTRACT

A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 13/367,382 filed Feb. 7, 2012, and included herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor device. In particular, the present invention relates to a semiconductor device with a pull backed gate structure.

2. Description of the Prior Art

In recent years, as various kinds of consumer electronic products are constantly improved and miniaturized, the size of semiconductor components have reduced accordingly, in order to meet the requirement of high integration, high performance, and low power consumption.

With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin structure of the silicon substrate, the channel region is therefore accordingly more effectively controlled. The drain-induced barrier lowering (DIBL) effect and the short channel effect are therefore reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.

In conventional processes for fabricating fin FET devices, the sidewalls of the gate and fin structures are covered with a spacer. The material of said spacer tends to remain on the sidewalls of the fin structure, and the poor gap filling capacity makes it hard to fill the recess or the trench structure during the formation of said spacer. Furthermore, the presence of a spacer will hinder the following ion implantation process for forming lightly doped drain (LDD), because the dopants will be blocked by the spacer and will be hard to be implanted in the sidewalls of the fin structures. Thus, the gate device formed by this conventional process may induce a large electric field gradient and impact the electrical properties of the gate device.

Accordingly, the present invention is directed to improve the conventional gate device in the semiconductor structure and the forming process thereof, in order to further enhance the performance of the devices.

SUMMARY OF THE INVENTION

To improve the above-mentioned drawbacks of the prior art, a new semiconductor structure and a method for fabricating the same is provided. The method of the present invention overcomes the problem of the dopants being easily blocked by the spacer during the ion implantation process by forming a lightly doped drain (LDD) structure after the gate pullback process. Furthermore, the electrical properties of gate devices formed by this method are further improved by using low-K material to form the spacers after the formation of said lightly doped drain.

The object of the present invention is to provide a non-planar semiconductor structure comprising a substrate, at least one fin structure on said substrate, a gate covering parts of said fin structures and parts of said substrate, a plurality of epitaxial structures covering said fin structures at both sides of said gate and being separated from said gate, wherein each of said gate, said epitaxial structure, and said fin structure define a recess, a source and a drain formed respectively in said fin structures and said epitaxial structures at both sides of said gate, lightly doped drains formed respectively in said fin structures between said gate and said epitaxial structure at both sides of said gate, and a spacer formed on the sidewalls of said gate and said epitaxial structures, wherein the portion of said spacer filling in said recesses is leveled with the top surface of said epitaxial structures.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

FIGS. 1-14 are cross-sectional views illustrating the flow of a non-planar semiconductor process in accordance with one embodiment of present invention;

FIG. 15 is a prospective view illustrating the gate device formed by the process of present invention;

FIGS. 16-21 are cross-sectional views illustrating the flow of a planar semiconductor process in accordance with another embodiment of present invention; and

FIGS. 22-25 are cross-sectional views illustrating the flow of a replacement metal gate process in accordance with one further embodiment of present invention.

It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

The embodiments will now be explained with reference to the accompanying drawings to provide a better understanding of the process of the present invention, wherein FIGS. 1-14 are cross-sectional views illustrating the flow of a non-planar semiconductor process in accordance with one embodiment of the present invention; FIG. 15 is a prospective view illustrating the gate device formed by the process of the present invention; FIGS. 16-21 are cross-sectional views illustrating the flow of a planar semiconductor process in accordance with another embodiment of the present invention; and FIGS. 22-25 are cross-sectional views illustrating the flow of a replacement metal gate (RMG) process in accordance with one further embodiment of the present invention.

First, please refer to FIGS. 1-15. Those figures illustrate sequentially the flow of a non-planar semiconductor process. The non-planar semiconductor process of the present invention comprises fabricating a fin field-effect transistor (Fin FET) or a tri-gate MOSFET. In a first embodiment, bulk silicon is used as a substrate. First, as shown in FIG. 1, a substrate 100 (ex. Si substrate) is provided as the base of the whole semiconductor structure. Substrate 100 may be provided with already predetermined NMOS regions and PMOS regions and corresponding P-wells and N-wells. Subsequently, a patterned mask layer 102 is formed on the substrate 100 as the etching mask for the following etching process that will form 3D fin structures, wherein the mask layer 102 may include a single material layer or a plurality of stacked material layers, such as a pad oxide layer 104 (ex. silicon oxide) and a nitride layer 106 (ex. silicon nitride) formed on pad oxide layer 104. The mask layer 102 may be patterned by performing a photolithographic process and an etching process El on a deposited material so as to expose parts of the substrate 100. After patterning the mask layer 102, as shown in FIG. 2, another etching process is performed subsequently by using said patterned mask layer 102 as a mask to transfer the pattern defined by the mask layer 102 to the substrate 100, thereby forming protruding and parallel fin structures 108 a and 108 b. In this embodiment, the number of fin structures defined by the mask layer 102 is two, but is not limited thereto.

After the formation of the fin structures 108 a and 108 b, as shown in FIG. 3, an isolation structure 110 is subsequently formed between each of the fin structures by successively performing a deposition, a planarization, and a back etching process. For example, the isolation structure 110 may be an oxide layer, which may be formed by shallow trench isolation technologies, for example: first forming an isolation layer (not shown) to cover fin structures 108 a and 108 b, then performing an etch-back process to form the isolation structure 110. This way, the two fin structures 108 a and 108 b are formed on the substrate 100 and an isolation structure 110 is formed between the fin structures 108 a and 108 b. In one preferred embodiment, the width of the fin structures 108 a and 108 b is about 20 nm, while the height of the fin structures 108 a and 108 b protruding out of the isolation structure 110 is about 30 nm. The mask layer 102 on the fin structures may be removed to form a tri-gate MOSFET. In another embodiment, the mask layer 102 may be kept to form a fin FET in a following process.

In addition to the example of using bulk Si as the substrate, in another embodiment, silicon-on-insulator (SOI) may be used as the substrate. As shown in FIG. 4, a SOI substrate is first provided comprising: a substrate 202, a bottom oxide layer 204 on the substrate 202, and a silicon layer 206 on bottom oxide layer 204, wherein said silicon layer 206 is a single crystal Si layer used to form various semiconductor devices. Subsequently, as shown in FIG. 5, a silicon layer 206 is patterned with a mask layer to form the fin structures 208 a, 208 b and expose parts of the bottom oxide layer 204. In this embodiment, the two fin structures 208 a and 208 b are formed on an isolation structure (i.e. the bottom oxide layer 204), thus good isolation may be provided for the gate elements formed in following process, and the STI process may be skipped. The method of patterning the silicon layer 206 is well-described in the previous embodiment; therefore no unnecessary detail will be given herein for simplicity.

For the above-mentioned two embodiments using bulk Si and SOI respectively as the substrate, as shown in FIG. 1, the isolation structure 110 in bulk Si is formed only between each fin structures (ex. 108 a and 108 b), while the bottom oxide layer 204 in SOI substrate 200, as shown in FIG. 5, is formed under the fin structures (ex. 108 a and 108 b). However, this difference will not influence the following processes.

The bulk Si can be used as the substrate to explain the process of present invention in following processes. As shown in FIG. 6, a gate structure 112 is formed on a part of the isolation structure 110 and a part of the fin structures 108 a and 108 b. Said gate structure 112 traverses multiple fin structures, thereby constructing a non-planar gate device. The gate structure 112 may be formed by a series of processes such as deposition, chemical mechanical polishing (CMP) and patterning. The gate structure 112 may comprise a gate dielectric layer 114 (such as SiO₂ or high-k material) on parts of the isolation structure 100 and parts of the fin structure 108 a and 108 b, a gate electrode 116 on said gate dielectric layer 114, and a cap layer 118 on said gate electrode 116. The forming methods of these material layers are well-known in the art, and are not described herein.

In the present invention, a gate pullback step will be performed in the following processes to trim the critical dimension (CD) of gate structure 112, and a replacement metal gate process may be optionally performed after the formation of the gate device to replace the gate electrode with at least one work function metal plus at least one low-resistivity metal. For this purpose, take gate first process for example, the material of the gate electrode 116 may be selected from the group of poly-Si, salicide, metal, or the combination thereof. On the other hand, take gate last process for example, the material of the gate electrode 116 may be selected from the group of poly-Si, SiN or SiON, or advanced pattern film (APF) provided by Applied Materials, or a combinations thereof, while the corresponding cap layer 118 may be of SiN or SiO₂. The detailed description of the above-mentioned pullback process and the optional replacement metal gate process will be explained in the following embodiment.

After the formation of the gate structure 112, as shown in FIG. 7, an epitaxy process E2 is performed to form epitaxial structures 120 a and 120 b surrounding the gate structure 112. In this step, the epitaxial structure 120 a and 120 b are formed on the surface of the fin structure 108 a and 108 b. The function of the epitaxial structures 120 a and 120 b is to increase the volume and the surface area of the fin structures 108 a and 108 b (that serve as source/drain regions), so that the metal layers formed in later processes, such as titanium (Ti), cobalt (Co), nickel (Ni), etc. can more easily cover the surface of the epitaxial layers 120 a and 120 b for performing self-aligning salicide processes. The material of the epitaxial structures 120 a and 120 b may include silicon germanium (SiGe), silicon carbide (SiC), a combination thereof, or other III-V compounds, depending on the type of multi-gate FET (such as PMOS or NMOS).

In another embodiment of the present invention, the fin structures 108 a and 108 b on epitaxial structure may be a stress source to strain the abutted silicon channel in order to increase the mobility of the electrons (e−) and the holes (h+) in the silicon channel. In this embodiment, as shown in FIG. 8, an etching process E3 is first performed to etch parts of the fin structure 108 a and 108 b at both sides of the gate 112. The etching process E3 has different etching rate in different crystalline planes, so that a recess R will be formed on the sidewall of the fin structures 108 a and 108 b respectively. The etching process E3 may include a dry etching process and a wet etching process, or only a wet etching process. For example, the wet etching process comprises etching by an etchant containing ammonia, hydrogen peroxide and water. Alternately, the etchant may be ammonia etchant, methyl ammonium hydroxide etchant, hydroxide etchant, or ethylene diamine pyrocatechol etchant, etc.

Following the embodiment above, after forming the recess R by etching the fin structures 108 a and 108 b, as shown in FIG. 9, an epitaxy process E4 is performed to form conformably epitaxial structures 120 a and 120 b having hexagon-shaped profile structures. Depending on the type of multi-gate FET, the epitaxial structures 120 a and 120 b may include a SiGe epitaxial layer (for PMOS transistor) or a SiC epitaxial layer (for NMOS transistor). The formed epitaxial structures 120 and 120 b may exert a stress on the lattice of the fin structures 108 a and 108 b under the gate structure 112, to form a strained silicon channel, thereby attaining the efficacy of increasing carrier mobility.

Please note that in the example where common poly-Si is used as the material for the gate electrode 116, an additional gate pre-pullback process will be performed on the poly-Si gate electrode 116 before the epitaxy process in order to avoid the epitaxial structure 120 to simultaneously grow on the gate structure 112 during the epitaxy process E2 or E4. This issue may bridges the gate structures 112 and fin structures 108. The gate pre-pullback process may include an oxidizing treatment or a nitridizing treatment to form an oxide layer or a nitride layer on the exposed surface of the gate electrode 116. This way, the epitaxial layer will not grow on poly-Si gate electrode 116, thus preventing the bridging of gate structures 112 and fin structures 108.

After the formation of the gate structures and the fin structures, the following embodiment will be based on the structure shown in FIG. 7 to explain the subsequent steps of the present invention with reference to the exemplified cross-sectional views in order to provide a better understanding for the reader. FIG. 10 is a cross-sectional view taken from the line A-A′ in FIG. 7, which illustrates a non-planar semiconductor structure comprising a fin structure 108, a gate structure 112 on said fin structure 108, and an epitaxial structures 120 covering the fin structures 108 at both sides of the gate structure 112, wherein said gate structure 112 includes a cap layer 118, a gate electrode 116, and a gate oxide layer 114.

In the present invention, as shown in FIG. 10, an ion implantation process E5 is performed to implant adequate dopants in the epitaxial structures 120 and the fin structures 108 after the formation of the epitaxial structures 120, thereby forming predetermined source/drain areas 122 a/ 122 b in said fin structures 108. The dopants to be implanted depended on the type of semiconductor device; it may be n-type dopant such as phosphor (P) or arsenic (As) (for NMOS transistor), or p-type dopant such as boron (B) (for PMOS transistor).

After the formation of the source/drain regions 122 a/ 122 b, as shown in FIG. 11, a gate pullback process E6 is performed to trim the critical dimension (CD) of the gate structure 112. The gate pullback process E6 maybe a wet etching process, which may etch the sidewalls of the gate structure 112 and reduce the critical dimension of gate structure. For example, when the material of the gate electrode in the dummy gate is poly-Si, SiN or SiON, or advanced pattern film (APF) provided by Applied Materials, the etchant for wet etching may be diluted KOH, HF/EG (ethylene glycol mix chemical) or low temperature H₃PO₄, respectively. O₂ plasma may also be used. The gate pullback process E6 may only etch the sidewalls of the gate structure 112 without damaging the epitaxial structures 120 or trimming the height of the gate structure 112 thanks to the protection of the cap layer 118. The gate pullback process E6 not only reduce the CD of the gate structure 112 between the epitaxial structures 120, but also separate the gate structure 112 and the epitaxial structure 120 at both sides to expose the fin structure 108 thereunder, thereby forming a recess structure 126.

After the gate pullback process E6, please refer to FIG. 12. An ion implant process E7 is subsequently performed to implant dopants into the exposed fin structure 108, thereby forming lightly doped drains (LDD) 128 at both sides of gate electrode 116. Similar to the fabrication of the source/drain regions 122 a/ 122 b, the material of the implanted dopants depends on the type of semiconductor device: it may be n-type dopants such as phosphor (P) or arsenic (As) (for NMOS transistor), or p-type dopants such as boron (B) (for PMOS transistor). In the present invention, since the dopants may be implanted into the fin structures 108 without being blocked by the spacer, the doping concentration and the doping profile of the formed lightly doped drain 108 may be precisely controlled.

In a further embodiment of the present invention, a salicide process may be performed to form a salicide layer 124 on the surface of the epitaxial structures 120 and the gate structure 112 after the formation of the epitaxial structures 120, wherein the salicide process may include a post clean process, a metal depositing process, an annealing process, a selective etching process, or a test process, etc. The forming process of the salicide layer is well-known in the art, thus no unnecessary detail is given herein for simplicity. Alternatively, the above-mentioned salicide process maybe performed after the following replacement metal gate process or after the formation of contact holes.

After the formation of the lightly doped drain 128, as shown in FIG. 13, the whole substrate is blanket-deposited with a material layer 130 as the material source for a spacer in a following process. Please note that, in one preferred embodiment of the present invention, the material layer 130 may be formed by spin-on-glass (SOG) process or flowable CVD (FCVD). Furthermore, low-k material (ex. polysilozane) may be adopted in those processes to form the material layer 130. In further embodiments of the present invention, a liner layer (ex. Si₃N₄, SiON, or SiCN layer, not shown) may be formed on the substrate before the formation of the material layer 130 to facilitate the formation of the material layer 130 on the substrate, and improve the reliability of the gate device.

Please refer to FIG. 14. After the formation of the material layer 130, an etching process E8 is performed to etch the material layer 130, thereby forming a spacer 132 on the sidewalls of the gate structure 112 and the epitaxial structure 120. The etching process E8 may comprise an etch-back process for the material layer 130 and a dry etching process to form the spacer 132. The etch back process may etch the original material layer 130 until the thickness of the material layer 130 reaches a predetermined value, while the dry etching process is for etching the remaining material layer 130 to the spacer 132. Please note that, in a preferred embodiment of the present invention, the formed spacer 132 is filled up the recess 126 between the gate structure 112 and the epitaxial structures 120 and the spacing between the fin structures 108. Furthermore, a portion 132 a of the spacer 132 is leveled with the abutted epitaxial structures 120.

Please refer to FIG. 15. FIG. 15 is a prospective view illustrating the gate device formed by the process of the present invention. As shown in the figure, for the final structure formed in present invention, it is possible that not all of the sidewalls of the gate structure 112 are covered by the spacer 132 due to the etching process. In this embodiment, only the sidewalls that are lower than the level of the top surface of the epitaxial structures 120 will be covered by the spacer 132, and the spacer filled in the recess 126 will be leveled with the epitaxial structures 120.

To sum up the above embodiment, in the present invention, it is possible to form a spacer with low-K material by using a SOG process or a FCVD process. The parasite capacitance may be efficiently reduced by forming the spacer structure with such low-K material. Moreover, the recess 126 between the gate structure 112 and the epitaxial structures 120 may be filled completely with the formed spacer due to the excellent gap-filling capacity of the processes.

The process flow of the present invention may be applied in the fabrication of planar semiconductor device. In following embodiments, the flow for planar semiconductor devices with the processes of the present invention will be explained with reference to FIGS. 16-20. First, please refer to FIG. 16, a substrate 300 is provided as the base of a whole semiconductor structure. The substrate 300 may be, but not limited to, a silicon substrate, an epitaxial silicon substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator substrate, etc. The substrate 300 may be provided with already predetermined NMOS regions and PMOS regions, and corresponding P-wells and N-wells. Subsequently, a patterned gate structure 302 is formed on the substrate 300. The process for forming the gate structure 302 comprises the steps of: forming a gate oxide layer 304, a gate electrode 306, and a cap layer 308 successively on the substrate 300, patterning the cap layer 308, performing an etching process on the gate electrode 306 by using the patterned cap layer 308 as a mask to form the patterned gate electrode 306 and a gate oxide layer 304. The method for forming the gate electrode and the gate oxide layer is well-known in the art, therefore no unnecessary detail is given herein for simplicity.

In the present invention, a gate pullback step is performed in the following process to trim the critical dimension (CD) of the gate structure 302, and a replacement metal gate process may be optionally performed after the formation of the gate device to replace the gate electrode with at least a work function metal and at least a low-resistivity metal. For this purpose, the material of the gate electrode 306 may be poly-Si, SiN or SiON, or advanced pattern film (APF) provided by Applied Materials, or a combinations thereof, while the corresponding cap layer 118 may be SiN or SiO₂. The detailed description of above-mentioned pullback process and optional replacement metal gate process will be explained in a following embodiment.

After defining the pattern of the gate structure 302, as shown in FIG. 16, an etching process E9 is performed to form recesses 310 in the substrate 300 for the formation of epitaxial structures in a following process. The etching process E9 may include a first dry etching process and a first wet etching process, wherein the first dry etching process provides downward etching by using SF6-based etchant or NF₃-based etchant, which are etch-selective to the substrate 300. The first wet etching process provides downward etching and lateral etching, thereby forming a concave surface 310 a concaved in the direction towards the gate structure 302 in the substrate 300.

Please note that the structure shown in the cross-sectional view of FIG. 16 is similar to the structure shown in previous FIG. 8 (etching the fin structure 108 first and then growing the epitaxial structure 120), thus the steps described after FIG. 16 may also be applied to the process flow of the structure shown in FIG. 8.

In the following process, please refer to FIG. 17, a selective epitaxial growth (SEG) process is performed to grow epitaxial structures 312 in the recess 310 of previous step. The epitaxial structure 312 is used as a stress source for straining the abutted silicon channel. In the present embodiment, the epitaxial structure 312 may be made of SiGe (for PMOS transistor) or SiC (for NMOS transistor) which will exert a stress on the abutting silicon channel region 10 a, thereby improving the carrier mobility.

Please refer again to FIG. 18, in the embodiment of the present invention, an ion implantation process is subsequently performed on the epitaxial structure 312 formed in previous steps. This process may implant n-type dopants (ex. P, As, or Sb), p-type dopants (ex. B or BF₂) combining with other common dopants (ex. C, N, F, Ge, or Si) into the epitaxial structure 312 in corresponding NMOS regions or PMOS regions, thereby defining the source/drain regions 314 a/ 314 b in the epitaxial structure 312 at both sides of the gate structure 302.

Please refer no to FIG. 19. Similarly, after the formation of source/drain regions 314 a/ 314 b, a gate pullback process Ell is performed to trim the critical dimension (CD) of the gate structure 302. The gate pullback process Ell may be a wet etching process which may etch the sidewalls of the gate structure 302; therefore the critical dimension of the gate structure may be reduced. Depending on the material of the gate electrode 306, the etchant for wet etching may be diluted KOH, HF/EG (ethylene glycol) mix chemical, low temperature H₃PO₄. O₂ plasma may also be used. The gate pullback process Ell may only etch the sidewalls of the gate structure 302 without damaging the epitaxial structure 312 or trimming the height of the gate structure 302 thanks to the protection of cap layer 308. The gate pullback process E6 will reduce the CD of the gate structure 302 between the epitaxial structures 312, thereby exposing the fin structure 108 thereunder.

Similarly, please note that in the example where common poly-Si is used as the material for the gate electrode 306, a gate pre-pullback process is performed on the poly-Si gate electrode 306 before the epitaxy process, in order to prevent the epitaxial structure 312 from simultaneously growing on the gate structure 302 during the epitaxy process, and bridging the gate structures 302 and the substrate 300. The gate pre-pullback process may include an oxidizing treatment or a nitridizing treatment to form an oxide layer or a nitride layer (not shown) on the exposed surface of the gate electrode 306. This way, the epitaxial structure will not grow on the poly-Si gate electrode 306, thus preventing the bridging of the gate structures 302 and the substrate 300.

After the gate pullback process E11, please refer to FIG. 20, an ion implantation process E12 is performed to implant dopants into the exposed substrate 300 b; thereby forming lightly doped drains (LDD) 318 at both sides of the gate structure 302. Similar to the fabrication of source/drain regions 314 a/ 314 b, the material of the implanted dopant depends on the type of semiconductor device: it may be n-type dopants such as phosphor (P) or arsenic (As) (for NMOS transistor), or p-type dopants such as boron (B) (for PMOS transistor). In the present invention, since the spacer is not formed yet on the gate structure 302 at this stage, the dopants may be implanted into the substrate 300 b without being blocked by the spacer. Moreover, for the pull backed gate structure, an optional multiple tilt angle implantation may be performed to further precisely control the doping concentration and the doping profile of the formed lightly doped drain 108.

After the formation of the lightly doped drains 318, as shown in FIG. 21, the spacer 320 is formed on the sidewalls of the gate structure 302. The spacer 320 may be formed by depositing and etching a material layer. This process is well-described in the previous embodiments and no unnecessary additional detail is given herein for simplicity.

In a further embodiment of the present invention, a salicide process may be performed to form the salicide layer 316 on the surface of the source/drain regions 314 a/ 314 b after the formation of the spacer 320. Alternatively, the above-mentioned salicide process may be performed after the following replacement metal gate process or after the formation of contact holes. The salicide process may include a post cleaning process, a metal depositing process, an annealing process, a selective etching process, or a test process, etc. The forming process of salicide layer is well-known in the art, and is not described further herein. A full gate device is, therefore, completed.

In the following embodiment, a replacement metal gate (RMG) process (i.e. gate last process) is explained with references to the FIGS. 22-25. The replacement metal gate process is an advantageous process, which is able to avoid processes of high thermal budget and to provide wider material choices, thus gradually replacing the gate first processes. Please note that the replacement metal gate process may be applied to both of the above-described non-planar and planar semiconductor processes without any process incompatibility issues. FIGS. 22-25 are based on the completed structure shown in FIG. 14. Some components shown in FIG. 22-25 may be different from the ones shown in FIG. 14, but the entire process will not be influenced by those differences.

Please refer to FIG. 22. FIG. 22 illustrates the completed semiconductor device shown in the embodiment of FIG. 14, which comprises a gate structure 112, a fin structure 108, and an epitaxial structure, etc. A deposition process is first performed on the substrate to selectively grow a contact-etch stop layer (CESL, not shown) and an inter-layer dielectric layer (ILD) 134. The ILD layer 134 is blanket-deposited on the substrate (including the region of the whole gate structure 112 and the epitaxial structure 120) and has a predetermined thickness over the gate structure 112.

Please refer subsequently to FIG. 23. After the formation of the ILD layer 134, parts of the ILD layer 134 and of the cap layer 118 are removed by a planarization process E13 to expose the gate electrode 116 in the gate structure 112. The gate electrode 116 serves as a dummy gate in this embodiment and will be removed in a following process.

After the planarization process E13, as shown in FIG. 24, an etching process E14 is performed to etch the exposed gate electrode 116. The gate electrode 116 is then completely removed in this step to expose the gate dielectric layer 114 thereunder. A gate trench 136 is formed in this process to provide a space for the gate metal material.

It is worth noting that the present embodiment maybe integrated with the high-K first process. In this kind of process, the gate dielectric layer 114 includes high-k materials, such as rare earth metal oxides. The gate dielectric layer 114 in this case is formed before the patterning of the gate structure 112 and will be patterned simultaneously with the gate structure 112. The above-mentioned high-k gate dielectric layer 114 can include material selected from the group consisting of hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO₄), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), tantalum oxide (Ta₂O₅), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), strontium titanate oxide (SrTiO₃), zirconium silicon oxide (ZrSiO₄), hafnium zirconium oxide (HfZrO₄), strontium bismuth tantalate, (SrBi₂Ta₂O₉, SBT), lead zirconate titanate (PbZr_(x)Ti_(1-x)O₃, PZT), and barium strontium titanate (Ba_(x)Sr_(1-x)TiO₃, BST). Additionally, an interfacial layer (not shown) can be formed between the high-k gate dielectric layer 104 and the substrate 100. After forming the first gate trench 150 and the second gate trench 152, an etch stop layer 108 can be formed on the bottom barrier layer 106 in both of the first gate trench 150 and the second gate trench 152. The etch stop layer 108 can include tantalum nitride (TaN), but not limited to this. In this embodiment, a bottom barrier layer (ex. a TiN layer) and an etching stop layer (ex. a TaN layer) may be additionally formed on the gate dielectric layer 114 in the gate trench 136. No unnecessary detail is given herein for simplicity.

On the other hand, the present embodiment may also be integrated with the high-K last process. In this process, a high-K gate dielectric layer (as the gate dielectric layer 138 shown in FIG. 25) is formed on the substrate (including the surface of the gate trench 136) after removing of the dummy gate and forming the gate trench 136, rather than formed before the patterning of the gate structure 112. Similarly, a bottom barrier layer (ex. a TiN layer) and an etching stop layer (ex. a TaN layer) may be additionally formed on the gate dielectric layer 114 in the gate trench 136. No unnecessary detail is given herein for simplicity.

Please refer again to the FIG. 25, after the formation of the gate dielectric layer 138, a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD) is performed to form a work function metal layer (WFM, 140) in the gate trench 136. The work function metal layer 140 may be a p-type work function metal layer and exemplarily includes TiN, TaN, titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but not limited to this. Alternatively, the work function metal layer 140 may be an n-type work function metal layer and exemplarily includes titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), or hafnium aluminide (HfAl), but not limited to this. In addition, the work function metal layer 140 may be a single-layered structure or a multi-layered structure. For example, the work function metal layer 140 may comprises a plurality of different work function metal layers, to optimize the electrical properties of the gate device.

After the formation of work function metal layer 140, a top barrier layer (not shown) may be optionally formed in gate trench 136, and a filling metal layer 142 is then formed thereon. The filling metal layer 168 is formed to fill up the gate trench 136. The filling metal layer 142 includes materials with low resistivity and superior gap-filling characteristics, such as Al, W, Cu, TiAl, or titanium aluminum oxide (TiAlO), but not limited to this.

After forming the gate electrode above, one or more planarization process is finally performed, such as a CMP process, to remove the unnecessary filling metal layer 142, work function metal layer 140, and gate dielectric layer 138, thereby completing the fabrication of a replacement metal gate structure. In addition, another embodiment of the present invention may continue the process after the formation of the replacement metal gate structure. This process involves the steps of completely removing the ILD layer 134 and the CESL layer, and then forming another ILD layer and a CESL layer (not shown) to ensure that the CESL layer can provide a sufficient and adequate compressive or tensile stress. Please note that the above-described replacement metal gate (RMG) process is only an exemplified embodiment, which briefly explain the basic steps for fabricating the various components in the replacement metal gate structure. Some repeating steps, or necessary components, may be omitted in this description without obscuring the principles of the RMG process combined with the semiconductor process of the present invention.

To sum up the processes and all technical features provided in the above embodiments of the present invention, a novel non-planar semiconductor structure is accordingly provided in the present invention. The non-planar semiconductor structure is provided with technical features formed or embodied by the process flow of the present invention, as shown in FIG. 9 and FIG. 14, comprising: a substrate 100, at least one fin structure 120 on the substrate 100; a gate 112 covering parts of the fin structures 108 and parts of the substrate 100, a plurality of epitaxial structures 120 covering the fin structures 120 at both side of the gate 112 and being separated from the gate 112, wherein each of the gate 112, the epitaxial structures 120, and the fin structures 108 define a recess 126, a source 122 a and a drain 122 b, formed respectively in the fin structures 108 and the epitaxial structures 120 at both sides of the gate 112; lightly doped drains formed respectively in the fin structures 108 between the gate 112 and the epitaxial structures 108 at both sides of the gate 112, and a spacer 12 formed on the sidewalls of the gate 112 and the epitaxial structures 108, wherein the portion of the spacer 132 filling in the recess 126 is leveled with the top surface of the epitaxial structures 120.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

What is claimed is:
 1. A non-planar semiconductor structure, comprising: a substrate; at least one fin structure on said substrate; a gate covering parts of said fin structures and part of said substrate such that said fin structure is divided into a channel region stacking with said gate and source/drain regions at both sides of said gate; a plurality of epitaxial structures covering on said source/drain regions of said fin structures, a recess is provided between said channel region of said fin structure and said epitaxial structure; and a spacer formed on the sidewalls of said gate and said epitaxial structures, wherein the portion of said spacer filling in said recesses is flush with the top surface of said epitaxial structures.
 2. A non-planar semiconductor structure according to claim 1, wherein said fin structure further comprises lightly doped drains formed respectively between said channel region and said source/drain region.
 3. A non-planar semiconductor structure according to claim 1, wherein the material of said spacer is low-K material, such as polysilozane.
 4. A non-planar semiconductor structure according to claim 1, wherein the material of said substrate comprises silicon substrate, epitaxial silicon substrate, silicon germanium (SiGe) substrate, silicon carbide (SiC) substrate, or silicon-on-insulator substrate.
 5. A non-planar semiconductor structure according to claim 1, wherein the material of said epitaxial structure comprises silicon germanium (SiGe), silicon carbide (SiC), or a combination thereof.
 6. A non-planar semiconductor structure according to claim 1, wherein said gate comprises gate dielectric layer, gate electrode and cap layer.
 7. A non-planar semiconductor structure according to claim 6, wherein the material of said gate electrode is selected from the group of poly-Si, salicide, metal, SiN, SiON, advanced pattern film (APF), or a combinations thereof.
 8. A non-planar semiconductor structure according to claim 1, wherein said gate is a replacement metal gate.
 9. A non-planar semiconductor structure according to claim 8, wherein said replacement metal gate comprises gate dielectric layer, work function metal layer and filling metal layer.
 10. A non-planar semiconductor structure according to claim 9, wherein the material of said gate dielectric layer is high-K material, such as the material selected from the group consisting of hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO₄), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), tantalum oxide (Ta₂O₅), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), strontium titanate oxide (SrTiO₃), zirconium silicon oxide (ZrSiO₄), hafnium zirconium oxide (HfZrO₄), strontium bismuth tantalate, (SrBi₂Ta₂O₉, SBT), lead zirconate titanate (PbZr_(x)Ti_(1-x)O₃, PZT), and barium strontium titanate (Ba_(x)Sr_(1-x)TiO₃, BST).
 11. A non-planar semiconductor structure according to claim 9, wherein the material of said work function metal layer 140 comprises p-type work function metal layer such as TiN, TaN, titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), aluminum titanium nitride (TiAlN), or n-type work function metal layer such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), or hafnium aluminide (HfAl).
 12. Anon-planar semiconductor structure according to claim 9, wherein the material of said filling metal layer comprises Al, W, Cu, TiAl, or titanium aluminum oxide (TiAlO). 